The invention relates to an apparatus for measuring parasitic capacitances, which is used in particular in integrated circuits, such as, for instance, a semiconductor memory.
The increasing packing density leads in particular to interference effects resulting from conductor tracks in integrated circuits, referred to as parasitic interconnect capacitance, playing an increasingly major part. Since the conductor tracks themselves are designed to be increasingly smaller, the parasitic effects associated with components (in particular transistors) decrease more and more, but the effects caused by the conductor tracks generally do not. The latter effects therefore become increasingly important, and even small disruptions can lead to failures of integrated circuits in current technologies. A very accurate method is therefore required in order to be able to register disturbance effects, i.e., parasitic effects.
In determining parasitic effects, an extremely wide range of measuring methods is employed. For example, from James C. Chen et al., xe2x80x9cAn On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement Techniquexe2x80x9d, IEDM 96-69, IEEE, 0-7803-3393-4, it is known to connect a test structure and a reference structure to a voltage source and then to discharge the test structure and the reference structure again via a ground potential. In the process, the current flowing during the charging of the reference structure and the test structure is measured, and the difference is used to calculate a parasitic capacitance which is present in the test structure as opposed to the reference structure.
The test structure and the reference structure are constructed differently. It is possible both for the geometric form of the two structures to differ and their environment, and the test structure therefore has a different capacitance than the reference structure. This can be measured in the form of an additional charge during the charging or discharging of the test structure as compared with the reference structure. By using the difference between the capacitances determined, systematic errors arising from the components used for the circuit can also be minimized, since these occur to the same extent in the test and reference structures.
Furthermore, from the thesis by Stefan Sauter, Fakultxc3xa4t fxc3xcr Elektrotechnik und Informationstechnik, Technische Universitxc3xa4t Mxc3xcnchen, [Electrical Engineering and Information Technology Faculty, Technical University of Munich] chapter 5, it is known to measure extremely small parasitic capacitances with a novel sub-femtofarad method.
It is accordingly an object of the invention to provide an apparatus, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, in simple terms, provides for an improved apparatus for measuring parasitic capacitances.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for measuring parasitic capacitances of an integrated circuit, comprising:
a test structure having a first conductor and a second conductor;
a reference structure having a third conductor;
a first switch for selectively connecting the first conductor to a first voltage source and a second switch for selectively connecting the first conductor to ground potential;
a third switch for selectively connecting the third conductor to a second voltage source and a fourth switch for selectively connecting the third conductor to ground potential;
the reference structure having a fourth conductor connected to the third switch for selectively connecting the fourth conductor to the second voltage source and to the fourth switch for selectively connecting the fourth conductor to ground potential;
wherein a coupling capacitance between the first conductor and the second conductor substantially equals a coupling capacitance between the third conductor and the fourth conductor;
wherein the first, second, third, and fourth conductors are constructed such that the first and second conductors and the third and fourth conductors respectively have substantially equally large inherent capacitances; and
wherein the second conductor is directly connected to reference potential, such that the first conductor and the second conductor can assume mutually different potentials.
In other words, one characterizing feature of the invention is that the test structure and the reference structure are constructed from at least two pairs of conductors, the two conductors always being at the same potential in the reference structure and the two conductors in the test structure also being able to assume different potentials. A further characterizing feature of the invention is that the conductor to be tested and the associated conductor are arranged substantially in the same environment in relation to capacitive effects. In this way, the coupling capacitance between the two conductors is of equal size, so that the evaluation of the measured results is simplified.
In accordance with a preferred embodiment of the invention, the test structure and the reference structure are built up on a semiconductor material, which preferably has a semiconductor memory module. Use of the apparatus according to the invention in the area of integrated circuits which are built up on semiconductor materials constitutes an important field of application. In particular in the case of highly integrated modules such as semiconductor memory components, the measurement of parasitic capacitances is a significant method for characterizing the quality of the semiconductor memory component.
In a preferred embodiment, the first, the second, the third and the fourth conductor of the reference structure and the test structure are constructed in the form of conductor tracks, i.e., interconnects. Depending on the application, it is particularly advantageous to construct the four conductors identically. A particularly preferred embodiment of a conductor track consists in constructing a substantially rectangular conductor strip, which preferably has a uniform thickness and width over the entire length. In addition, the distance between the two conductor tracks of the test structure and of the reference structure, respectively, is preferably of equal size over the entire length. By means of this embodiment, particularly exact measured results are made possible.
The two conductors of the test structure and/or of the reference structure are preferably arranged in an environment which, apart from a predefined distance for the two conductors of the test structure and/or of the reference structure, is preferably identical in relation to capacitive effects. Thus, one-sided capacitive effects, which could occur in a conductor of the test structure or of the reference structure, are avoided.
In accordance with a concomitant feature of the invention, the first and second conductors and/or the third and fourth conductors are constructed as an intermeshing comb structure.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus for measuring parasitic capacitances on an integrated circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.